In its simplest terms, a computer system performs arithmetic operations, manipulates data, and performs tasks according to a series of instructions, called a "computer program." Virtually all computer systems include a central processing unit (CPU), a memory, an input/output (I/O), and a bus. In addition, there may be other devices (e.g., graphics accelerators, video chips, digital signal processors, sound cards, etc.) that are coupled onto the bus. Basically, the CPU executes the instructions of the computer program that is stored in memory. The I/O provides an interface between the user and the computer system. And the bus allows the different components of the computer system to communicate with each other.
The computer's bus plays a major role in the performance of the computer system. It is the bus, which conveys all the information and signals involved in the computer's operation. In most instances, it is imperative that large blocks of data be transferred as expeditiously as possible. For example, popular software applications prevalent today demand extremely fast updates of graphic images in order to move, resize, and update multiple windows without imposing unacceptable delays on the end user. Since the screen images are stored in video RAM, the processor must be able to update and move large blocks of data within video memory very quickly. This is especially the case when rendering images in real-time (e.g., video tele-conferencing, simulations, etc.). These applications are just a few examples which benefit substantially from fast bus transfer rates. Hence, it is imperative that data and information flow as fast as possible between the various components. Otherwise, a slow bus acts as a bottleneck which drags down the overall performance of the computer system, regardless of the microprocessor's speed or power.
In the past, a variety of bus standards have been implemented (e.g., ISA, EISA, Micro Channel bus, VLB, PCI, etc.). The ISA bus was the original standard of the PC industry. The EISA bus, the Micro Channel bus, and the VESA VL bus are all improvements over the ISA bus. However, the PC industry has presently adopted the PCI bus because of its high data transfer rate. The PCI bus can be accessed at clock speeds approaching that of the host processor's full native speed. However, notwithstanding the PCI's impressive speed characteristics, it can nevertheless become severely degraded as more and more devices are coupled onto the bus. The problem lies in the fact that bus access can only be granted to one device at any given time. If two or more devices request access to the bus, an arbitrator must arbitrate as to which device is allowed to transmit its data. Meanwhile, all other devices must wait until the bus again becomes available.
Furthermore, this problem is greatly compounded in those circumstances where devices are frequently required to transmit small amounts of data over the bus. For each write cycle, access to be bus must first be requested. Next, the request must be arbitrated. The requesting device must then wait for its access to be granted before data transmission can begin. Upon completion of data transmittal, the bus must be released. This entire process must be repeated for each write cycle, irrespective of how much data is actually transmitted. Clearly, much time and processing power is expended if only small amounts of data are transmitted during a write cycle. As a result, the throughput of the bus is greatly diminished.
Therefore, there is a need in the prior art for an apparatus and method for improving the utilization of a computer bus. It would be highly preferable if such an apparatus and method were to be compatible with existing bus standards, inexpensive to implement, and yet be highly effective. The present invention offers such a solution in the form a buffer that combines associated write operations in a manner whereby multiple writes can be transmitted in a single write cycle.